HYB39S256400T-10 データシートの表示（PDF） - Infineon Technologies

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HYB39S256400T-10

256 MBit Synchronous DRAM

Infineon Technologies 

HYB 39S256400/800/160T

256 MBit Synchronous DRAM

4. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.

5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.

6. These parameter account for the number of clock cycle and depend on the operating frequency

of the clock, as follows:

the number of clock cycle = specified value of timing period

(counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied

once the Self Refresh Exit command is registered.

Semiconductor Group

20

1998-10-01

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