Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
COM M AND TRUTH TABLE
COMMAND
CKE0 CKE0
MNEMONIC n-1
n
/S0
Deselect
DESEL
H
X
H
No Operation
NOP
H
X
L
Row Address Entry &
Bank Activate
ACT
H
X
L
Single Bank Precharge PRE
H
X
L
Precharge All Banks PREA
H
X
L
Column Address Entry
& Write
WRIT E
H
X
L
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
Column Address Entry
& Read
READ
H
X
L
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TERM
MRS
H
X
L
H
H
L
H
L
L
L
H
H
L
H
L
H
X
L
H
X
L
/RAS /CAS
X
X
H
H
A10 A0-9,
/WE BA0,1
/AP
note
11-12
X
X
X
X
H
X
X
X
L
H
H
V
V
V
L
H
L
V
L
X
L
H
L
X
H
X
H
L
L
V
L
V
H
L
L
V
H
V
H
L
H
V
L
V
H
L
H
V
H
V
L
L
H
X
X
X
L
L
H
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
H
H
L
X
X
X1
L
L
L
L
L
V2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
MIT-DS-0389-1.1
MITSUBISHI ELECTRIC
20.Nov.2000
6