MH64D72KLG-10 データシートの表示（PDF） - MITSUBISHI ELECTRIC

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MH64D72KLG-10

4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH64D72KLG-75,-10

4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

FUNCTION TRUTH TABLE for CKE

CKE0 CKE0

Current State n-1 n /S0 /RAS /CAS /WE Add

Action

Notes

SELF-

H X X X X X X INVALID

1

REFRESH

L H H X X X X Exit Self-Refresh (Idle after tRC)

1

L H L H H H X Exit Self-Refresh (Idle after tRC)

1

L H L H H L X ILLEGAL

1

L H L H L X X ILLEGAL

1

L H L L X X X ILLEGAL

1

L L X X X X X NOP (Maintain Self-Refresh)

1

POWER

DOWN

H X X X X X X INVALID

L H X X X X X Exit Power Down to Idle

L L X X X X X NOP (Maintain Self-Refresh)

ALL BANKS H H X X X X X Refer to Function Truth Table

2

IDLE

H L L L L H X Enter Self-Refresh

2

H L H X X X X Enter Power Down

2

H L L H H H X Enter Power Down

2

H L L H H L X ILLEGAL

2

H L L H L X X ILLEGAL

2

H L L L X X X ILLEGAL

2

L X X X X X X Refer to Current State =Power Down 2

ANY STATE H H X X X X X Refer to Function Truth Table

other than H L X X X X X Begin CLK Suspend at Next Cycle 3

listed above L H X X X X X Exit CLK Suspend at Next Cycle

3

L L X X X X X Maintain CLK Suspend

ABBREVIATIONS:

H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE0 Low to High transition will re-enable CK0 and other inputs asynchronously

. A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

MIT-DS-0389-1.1

MITSUBISHI ELECTRIC

20.Nov.2000

11

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