Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLG-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State /S0 /RAS /CAS /WE Address
RE-
H X X XX
FRESHING
L
H
H
HX
L H H L BA
L
H
L
X BA, CA, A10
L
L
H H BA, RA
L
L
H
L BA, A10
L
L
L
HX
Op-Code,
L
L
L
L
Mode-Add
MODE
H X X XX
REGISTER L H H H X
SETTING
L H H L BA
L
H
L
X BA, CA, A10
L
L
H H BA, RA
L
L
H
L BA, A10
L
L
L
HX
Op-Code,
L
L
L
L
Mode-Add
Command
Action
DESEL NOP (Idle after tRC)
NOP
NOP (Idle after tRC)
TERM
ILLEGAL
READ / WRITE ILLEGAL
ACT
ILLEGAL
PRE / PREA ILLEGAL
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Idle after tRSC)
NOP
NOP (Idle after tRSC)
TERM
ILLEGAL
READ / WRITE ILLEGAL
ACT
ILLEGAL
PRE / PREA ILLEGAL
REFA
ILLEGAL
MRS
ILLEGAL
Notes
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE0 was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MIT-DS-0389-1.1
MITSUBISHI ELECTRIC
20.Nov.2000
10