4Bit Single Chip Microcontroller
16
DMC42C1106
RAM DATA RETENTION TIMING
When STOP mode is released by RESETB input
STOP Mode
RAM Data retention
VDD
Internal Reset Operation
Stabilization Wait Time
Operation
Mode
STOP instruction execution
RESET
VDDDR
tSREL
tWAI
When STOP mode is released by interrupt signal
STOP Mode
RAM Data retention
VDD
VDDDR
STOP instruction execution
Stabilization Wait Time
Operation
Mode
tSREL
Interrupt Signal
tWAI
(Rising Edge)