CXD2548R データシートの表示（PDF） - Sony Semiconductor

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CXD2548R

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

(4) SCLK pin

XLAT

tDLS

tSPW

SCLK

Serial Read Out Data

(SENS)

···

1/fSCLK

MSB

···

Item

SCLK frequency

SCLK pulse width

Delay time

Symbol

fSCLK

tSPW

tDLS

Min.

500

15

Typ.

Max.

1

Unit

MHz

ns

µs

CXD2548R

LSB

(5) COUT, MIRR and DFCT pins

Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Symbol Min.

Typ.

Max. Unit Conditions

COUT maximum

operating frequency

fCOUT

40

kHz

∗1

MIRR maximum

operating frequency

fMIRR

40

kHz

∗2

DFCT maximum

operating frequency

fDFCTH

5

kHz

∗3

∗1 When using a high-speed traverse TZC

∗2

B

A

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.6 to 1.3V

• B = 25% or less

A+B

∗3 During complete RF signal omission

When settings related to DFCT signal generation are Typ.

– 11 –

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