CXD3511 データシートの表示（PDF） - Sony Semiconductor

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CXD3511

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3511Q

(3) Dot/line inversion support

When DLY_ON = 1, signal processing that supports dot/line inverted drive is performed. The output data is

output as shown in the figures below according to the Cond1 and Cond2 values. D and the dotted lines in the

figures indicate that the signal is delayed by 1H.

Cond1 Cond2

1

1

clk

port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18

port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19

port1 out

0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16 D1

port2 out

1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 IN2

Cond1 Cond2

0

1

clk

port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18

port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19

port1 out

0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17 D2

port2 out

1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 IN1

Cond1 Cond2

1

0

clk

port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18

port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19

port1 out

1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 IN1

port2 out

0.1 0.3 0.5 0.7 0.9 0.11 0.13 0.15 0.17 D2

Cond1 Cond2

0

0

clk

port1 in 1.0 1.2 1.4 1.6 1.8 1.10 1.12 1.14 1.16 1.18

port2 in 1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 1.19

port1 out

1.1 1.3 1.5 1.7 1.9 1.11 1.13 1.15 1.17 IN2

port2 out

0.0 0.2 0.4 0.6 0.8 0.10 0.12 0.14 0.16 D1

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