IDT7198S データシートの表示（PDF） - Integrated Device Technology

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IDT7198S

CMOS STATIC RAMs 64K (16K x 4-BIT) Added Chip Select and Output Controls

Integrated Device Technology 

IDT7198S/L

CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls

MILITARY TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)

tWC

ADDRESS

OE

CS1, 2

WE

DATAOUT

DATAIN

tAW

tAS

tWP (7)

tWR

tWHZ (6)

(4)

tOW (6)

tDW

tDH

DATA VALID

(4)

2985 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1)

tWC

ADDRESS

tAW

CS1, 2

tAS

tCW

tWR

WE

DATAIN

tDW

tDH

DATA VALID

2985 drw 11

NOTES:

1. WE, CS1 or CS2 must be HIGH during all address transitions.

2. A write occurs during the overlap (tWP) of a LOW WE, a LOW CS1 and a LOW CS2.

3. tWR is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, outputs remain in the high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified tWP.

6.4

7

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