MT90863AG データシートの表示（PDF） - Zarlink Semiconductor Inc
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MT90863AG Datasheet PDF : 46 Pages
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MT90863
Data Sheet
Pin Description
128 MQFP
Pin#
144 BGA
Pin#
Name
Description
30,50,67, C5,C9,D5,D7,
VDD +3.3 Volt Power Supply
79,97,107, D9,E10,F4,G10
117,127
,G11,H4,
K3,K4,K6,K8
K10,K11,L8
8,17,29,39, C6,C10,D4,D6,
49,68,78,8 D8,D10,E3,E4,
8,90,93,96, F10,F11,G2,
106,
G4,H10,J4,
116,126 J10,J11,K5
K7,K9,L3,L7
Vss
Ground
89
D12
C16i Master Clock (5 V Tolerant Input): Serial clock for shifting data in/out
on the serial streams. This pin accepts a 16.384 MHz clock.
91
D11
F0i Master Frame Pulse (5 V Tolerant Input): In ST-BUS mode, this
input accepts a 61 ns wide negative frame pulse. In CT Bus mode, it
accepts a 122 ns wide negative frame pulse. In HMVIP mode, it
accepts a 244 ns wide negative frame pulse.
92
B13
C4i/C8i HMVIP/CT Bus Clock (5 V Tolerant Input): When HMVIP mode is
enabled, this pin accepts a 4.096 MHz clock for HMVIP frame pulse
alignment. When CT Bus mode is enabled, it accepts a 8.192 MHz
clock for CT frame pulse alignment.
94
A13
F0o Frame Pulse (5 V Tolerant Output): A 244 ns wide negative frame
pulse that is phase locked to the master frame pulse (F0i).
95
C12
C4o C4 Clock (5 V Tolerant Output): A 4.096 MHz clock that is phase
locked to the master clock (C16i).
98-105,
108-115
C11, B12, B11,
A12, A11, B10,
A10, B9, A9,
C8, B8, A8, C7,
B7, A7, A6,
STio0 - 15 Serial Input Streams 0 to 15 / Frame Evaluation Inputs 0 to 15 (5 V
FEi0 - 15 Tolerant I/O). In 2 Mb/s and HMVIP modes, these pins accept serial
TDM data streams at 2.048 Mb/s with 32 channels per stream. In
4 Mb/s or 8 Mb/s mode, these pins accept serial TDM data streams at
4.096 or 8.192 Mb/s with 64 or 128 channels per stream respectively.
In Frame Evaluation Mode (FEM), they are frame evaluation inputs.
118-125
B6, A5, B5, A4, STio16 - 23 Serial Input Streams 16 to 23 (5 V Tolerant I/O). In 2 Mb/s or 4 Mb/s
B4, C4, A3, B3 FEi16 - 23 mode, these pins accept serial TDM data streams at 2.048 or
4.096 Mb/s with 32 or 64 channels per stream respectively. In HMVIP
mode, these pins have a data rate of 8.192 Mb/s with 128 channels
per stream. In Frame Evaluation Mode (FEM), they are frame
evaluation inputs.
128, A2, B2, A1, C3, STio24 - 31 Serial Input Streams 24 to 31 (5 V Tolerant I/O). These pins are only
1-7 C2, B1, D3, D2
used for 2 Mb/s or 4 Mb/s mode. They accept serial TDM data streams
at 2.048 or 4.096 Mb/s with 32 or 64 channels per stream respectively.
9
C1
TMS Test Mode Select (3.3 V Input with internal pull-up): JTAG signal
that controls the state transitions of the TAP controller.
10
D1
TDi Test Serial Data In (3.3 V Input with internal pull-up): JTAG serial
test instructions and data are shifted in on this pin.
8
Zarlink Semiconductor Inc.
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