MT90863 データシートの表示（PDF） - Zarlink Semiconductor Inc
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MT90863 Datasheet PDF : 46 Pages
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MT90863
Data Sheet
F0i
(HMVIP Frame)
C4i/C8i
(4.096MHz)
C16i
F0o
C4o
STio 0 - 15
STi/STo 0 - 15
(2Mb/s mode)
STio 16 - 23
(8Mb/s mode)
STi12/STo12
(Sub-rate
Switching)
Channel 0
0
7
6
Channel 0
1 076543210
Channel 0
0
1
0
Channel 31
1
0
7
Channel 127
65432107
Channel 127
1
0
Bit 1
Figure 6 - HMVIP Mode Timing for 2 and 8 Mb/s Data Streams
3.2 Local Interface
Three operation modes, 2 Mb/s, 8 Mb/s and Sub-rate Switching mode, can be selected for the local interface.
When 2 Mb/s mode is selected, STi0 to STi15 and STo0 to STo15 have a 2.048 Mb/s data rate. When 8 Mb/s mode
is selected, STi0 to STi3 and STo0 to STo3 have an 8.192 Mb/s data rate. When Sub-rate Switching mode is
selected, STi0 to STi11 and STo0 to STo11 have 2.048 Mb/s data with 64 kb/s data channels and STi12 and STo12
have a 2.048 Mb/s data rate with 16 kb/s data channels. Table 3 describes the data rates and mode selection for
the local interface.
3.3 Input Frame Offset Selection
Input frame offset selection allows the channel alignment of individual backplane input streams, that operate at
8.192 Mb/s (STio0-23), to be shifted against the input frame pulse (F0i). This feature compensates for the variable
path delays caused by serial backplanes of variable length. Such delays can be occur in large centralized and
distributed switching systems.
Each backplane input stream can have its own delay offset value by programming the input delay offset registers
(DOS0 to DOS5). Possible adjustment can range up to +4 master clock (C16i) periods forward with resolution of
half master clock period. See Table 10 and Table 11, and Figure 9,Figure 9 - for frame input delay offset
programming.
3.4 Output Advance Offset Selection
The MT90863 allows users to advance individual backplane output streams which operate at 8.192 Mb/s (STio0-
23) by half a master clock (C16i) cycle. This feature is useful in compensating for variable output delays caused by
various output loading conditions. The frame output offset registers (FOR0 & FOR1) control the output offset delays
for each backplane output stream via the OFn bit programming. Table 12 and Figure 10 detail frame output offset
programming.
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