MT90863AG データシートの表示（PDF） - Zarlink Semiconductor Inc
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MT90863AG Datasheet PDF : 46 Pages
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MT90863
Data Sheet
Pin Description (continued)
128 MQFP
Pin#
144 BGA
Pin#
Name
Description
63
L11
STi12 Serial Input Streams 12 (5 V Tolerant Input): In 2 Mb/s mode, this
input accepts data rate of 2.048 Mb/s with 32 channels per stream
respectively. In Sub-rate Switching mode, this pin accepts 2.048 Mb/s
with 128 channels per stream for Sub-rate switching application.
64-66
M12, M13, L12 STi13 - 15 Serial Input Streams 13 to 15 (5 V Tolerant Inputs): In 2 Mb/s mode,
these inputs accept a data rate of 2.048 Mb/s with 32 channels per
stream.
69
L13
ODE Output Drive Enable (5 V Tolerant Input): This is the output enable
control for the STo0 to STo15 serial outputs and STio0 to STio31 serial
bidirectional outputs.
70-73
K13, K12, J13,
J12
STo0 - 3
Serial Output Streams 0 to 3 (5 V Tolerant Three-state Outputs): In
2 Mb/s or Sub-rate Switching mode, these outputs have data rates of
2.048 Mb/s with 32 channels per stream respectively. In 8 Mb/s mode,
these outputs have data rates of 8.192 Mb/s with 128 channels per
stream
74-77,
80-83
H11, H13, H12, STo4 - 7, Serial Output Streams 4 to 11 (5 V Tolerant Three-state Outputs):
G13, G12, F13, STo8 - 11 In 2 Mb/s or Sub-rate Switching mode, these outputs have data rates
F12, E13
of 2.048 Mb/s with 32 channels per stream
84
E12
STo12 Serial Output Streams 12 (5 V Tolerant Three-state Output): In
2 Mb/s mode, this output has data rate of 2.048 Mb/s with 32 channels
per stream. In Sub-rate Switching mode, this pin has data rate of
2.048 Mb/s with 128 channels per stream for Sub-rate switching
application.
85-87
D13, E11, C13 STo13 - 15 Serial Output Streams 13 to 15 (5 V Tolerant Three-state Outputs):
In 2 Mb/s mode, these outputs have a data rate of 2.048 Mb/s with 32
channels per stream.
1.0 Device Overview
The Rate conversion Switch (MT90863) can switch up to 2,048 512 channels while also providing a rate
conversion capability. It is designed to switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local
interfaces. When the device is in the sub-rate switching mode, 2-bit wide 16 kb/s data channels can be switched
within the device. The device maintains frame integrity in data applications and minimum throughput delay for voice
application on a per channel basis.
The backplane interface can operate at 2.048, 4.096 or 8.192 Mb/s, arranged in 125 s wide frames that contain
32, 64 or 128 channels, respectively. A built-in rate conversion circuit allows users to interface between backplane
interface and the local interface which operates at 2.048 Mb/s or 8.192 Mb/s.
By using Zarlink’s message mode capability, the microprocessor can access input and output time-slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other ST-
BUS devices.
The frame offset calibration function allows users to measure the frame offset delay for streams STio0 to STio23.
The offset calibration is activated by a frame evaluation bit in the frame evaluation register. The evaluation result is
stored in the frame evaluation registers and can be used to program the input offset delay for individual streams
using internal frame input offset registers.
10
Zarlink Semiconductor Inc.
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