74LV04 データシートの表示（PDF） - NXP Semiconductors.
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74LV04 Datasheet PDF : 15 Pages
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NXP Semiconductors
4. Functional diagram
74LV04
Hex inverter
1
1
2
1 1A
3 2A
5 3A
9 4A
11 5A
13 6A
1Y 2
2Y 4
3Y 6
4Y 8
5Y 10
6Y 12
mna342
Fig 1. Logic symbol
1
3
4
1
5
6
1
9
8
1
11
10
1
13
12
mna343
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
mna341
Fig 3. Logic diagram (one gate)
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
14 VCC
13 6A
12 6Y
04
11 5A
10 5Y
9 4A
8 4Y
001aac441
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
terminal 1
index area
1Y 2
2A 3
2Y 4
3A 5
3Y 6
74LV04
VCC(1)
13 6A
12 6Y
11 5A
10 5Y
9 4A
001aah094
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
74LV04_3
Product data sheet
Rev. 03 — 4 December 2007
© NXP B.V. 2007. All rights reserved.
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