74VHC03TTR データシートの表示（PDF） - STMicroelectronics

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74VHC03TTR

QUAD 2-INPUT OPEN DRAIN NAND GATE

STMicroelectronics 

74VHC03

QUAD 2-INPUT OPEN DRAIN NAND GATE

s HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

) s POWER DOWN PROTECTION ON INPUTS

t(s s OPERATING VOLTAGE RANGE:

c VCC(OPR) = 2V to 5.5V

u s PIN AND FUNCTION COMPATIBLE WITH

d 74 SERIES 03

ro s IMPROVED LATCH-UP IMMUNITY

P s LOW NOISE: VOLP = 0.8V (MAX.)

te DESCRIPTION

le The 74VHC03 is an advanced high-speed CMOS

o QUAD 2-INPUT OPEN DRAIN NAND GATE

bs fabricated with sub-micron silicon gate and

double-layer metal wiring C2MOS technology.

O The internal circuit is composed of 3 stages

- including buffer output, which provides high noise

t(s) immunity and stable output.

This device can, with an external pull-up resistor,

c be used in wired AND configuration. This device

u can also be used as a led driver and in any other

d application requiring a current sink.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74VHC03MTR

74VHC03TTR

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Obsolete Pro Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 4

1/11

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