IDT72511L25J データシートの表示（PDF） - Integrated Device Technology

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IDT72511L25J

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

Write

DSA

1

2

RB

(or R/WB=1, DSB)

n+1

A→B Empty (2)

Flag

A→B Almost- (2)

Empty Flag

tWEF

tWAE

F

NOTES:

1. A→B FIFO is initially empty.

2. Assume the flag pins are programmed active LOW.

3. R/WA = 1.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Read

1

2

t REF

tRAEF

n+1

2668 drw 23

Figure 22. Empty and Almost-Empty Flag Timing for A→B FIFO, (n = programmed offset)

DSA

WB

(or R/WB=1, DSB)

(2)

B→A Almost-

Full Flag

(2)

B→A

Full Flag

Write

1

2

tWEF

t WFF

m+1

Read

1

NOTES:

1. B→A FIFO initially contains D – (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521.

2. Assume the flag pins are programmed active LOW.

3. R/WA = 1.

2

m+1

t RAFF

tRFF

2668 drw 24

Figure 23. Full and Almost-Full Flag Timing for A→B FIFO, (m = programmed offset)

5.32

27

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