IDT72511L25J データシートの表示（PDF） - Integrated Device Technology

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IDT72511L25J

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

A→B FIFO WRITE FLOW-THROUGH

DSA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DA0–DA17

ta LZ

DATA OUT

tbA

B→A

Full Flag(1)-

RB = 1 (or R/WB = 0)

WB (or DSB)

DB0–DB8

NOTES:

1. Assume the flag pin is programmed active LOW.

2. R/WA = 1

ta HZ

tRFF

tWFF

tb WPW

DATA INPUT

tb DS

tbDH

A→B FIFO READ FLOW-THROUGH

DSA

DA0–DA17

DATA INPUT

ta DS

taDH

A→B

Empty Flag (1-)

WB = 1 (or R/WB = 1)

RB (or DSB)

DB0–DB8

tWEF

taLZ

NOTES:

1. Assume the flag pin is programmed active LOW.

2. R/WA = 0

tbA

tb RPW

tREF

DATA OUT

tb DV

ta HZ

Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only

2668 drw 16

5.32

22

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