IDT72511L25J データシートの表示（PDF） - Integrated Device Technology

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IDT72511L25J

PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18

Integrated Device Technology 

IDT72511/IDT72521

BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY

A→B FIFO WRITE FLOW-THROUGH

DSA

DA0 - DA17

A→B

Full Flag(1)

RB (or DSB)

tb LZ

DB0 - DB17

DATA OUT

tbA

NOTES:

1. Assume the flag pin is programmed active LOW.

2. R/WA = 0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ta WPW

tRFF

tb DV

tb HZ

DATA INPUTS

taDS

ta DH

tWFF

B→A FIFO READ FLOW-THROUGH

DSA

taLZ

DA0 - DA17

B→A

Empty Flag (1)

WB (or DSB)

DB0 - DB17

DATA INPUT

tb DS

NOTES:

1. Assume the flag pin is programmed active LOW.

2. R/WA = 1

taA

t WEF

tbDH

taRPW

ta DV

DATA OUTPUT

ta HZ

tREF

2668 drw 15

Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only

5.32

21

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