74LV4094D データシートの表示（PDF） - NXP Semiconductors.
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74LV4094D Datasheet PDF : 20 Pages
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74LV4094
8-stage shift-and-store bus register
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK
output clamping current VO < 0.5 V or VO > VCC + 0.5 V
IO
output current
VO = 0.5 V to (VCC + 0.5 V)
0.5
+7 V
-
20 mA
-
50 mA
-
25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
SO16 package
-
+50 mA
50
- mA
65 +150 C
[1]
-
500 mW
(T)SSOP16 package
[2]
-
500 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[2] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC
VI
VO
Tamb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
Min
[1]
1.0
0
0
40
-
-
-
Typ
Max Unit
3.3
3.6 V
-
VCC
V
-
VCC
V
+25
+125 C
-
500 ns/V
-
200 ns/V
-
100 ns/V
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
74LV4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 March 2016
© Nexperia B.V. 2017. All rights reserved
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