AD5231 データシートの表示（PDF） - Analog Devices
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AD5231 Datasheet PDF : 14 Pages
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PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5231 PIN CONFIGURATION
O1 1
CLK 2
SDI 3
SDO 4
GND 5
VSS 6
T1 7
B1 8
16 O2
15 RDY
14 CS
13 PR
12 WP
11 VDD
10 A1
9 W1
AD5232 PIN CONFIGURATION
CLK 1
SDI 2
SDO 3
GND 4
VSS 5
A1 6
W1 7
B1 8
16 RDY
15 CS
14 PR
13 WP
12 VDD
11 A2
10 W2
9 B2
AD5231 PIN FUNCTION DESCRIPTION
# Name Description
1 O1
Non-Volatile Digital Output #1, ADDR(O1) =
1H, data bit position D0
2 CLK Serial Input Register clock pin. Shifts in one
bit at a time on positive clock CLK edges.
3 SDI Serial Data Input Pin.
4 SDO Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 24 clock pulses. This allows daisy-chain
operation of multiple packages.
5 GND Ground pin, logic ground reference.
6
VSS
Negative Supply. Connect to zero volts for
single supply applications.
7 T1
8 B1
Used as digital input during factory test mode.
Leave pin floating or connect to VDD or VSS.
B terminal of RDAC1.
9 W1
10 A1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H
A terminal of RDAC1.
11 VDD
Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
12 WP
Write Protect Pin. When active low WP
prevents any changes to the present contents
except retrieving EEMEM contents and
RESET.
13 PR
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 200H until EEMEM loaded with a
new value by the user (PR is activated at the
rising logic high transition)
14 CS
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
15 RDY Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
16 O2
Non-Volatile Digital Output #2, ADDR(O2) =
1H, data bit position D1.
AD5232 PIN FUNCTION DESCRIPTION
# Name Description
1 CLK Serial Input Register clock pin. Shifts in one
bit at a time on positive clock edges.
2 SDI Serial Data Input Pin. Shifts in one bit at a
time on positive clock CLK edges.
3 SDO Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 16 clock pulses. This allows daisy-chain
operation of multiple packages.
4 GND Ground pin, logic ground reference
5
VSS
Negative Supply. Connect to zero volts for
single supply applications.
6 A1
A terminal of RDAC1.
7 W1 Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H.
8 B1
B terminal of RDAC1.
9 B2
B terminal of RDAC2.
10 W2
11 A2
Wiper terminal of RDAC2,
ADDR(RDAC2) = 1H.
A terminal of RDAC2.
12 VDD
Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
13 WP
Write Protect Pin. When active low, WP
prevents any changes to the present contents,
except retrieving EEMEM content and
RESET.
14 PR
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 80H until EEMEM loaded with a new
value by the user (PR is activated at the logic
high transition).
15 CS
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
16 RDY Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
REV PrF
5
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
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