20
TO 0.01%
15
TO 0.1%
10
5
0
0
5
10
15
20
OUTPUT STEP SIZE – Volts
TPC 24. Settling Time vs. Step Size, Gain = 100
2.0
1.5
+IB
1.0
0.5
–IB
0
–0.5
–1.0
–1.5
–2.0
–125
–75
–25
25
75
TEMPERATURE – ؇C
125
175
TPC 25. Input Bias Current vs. Temperature
100V
100
90
AD621
2V
10
0%
TPC 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100 µV/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
INPUT
20V p-p
100k⍀
1%
G = 10
11k⍀
0.1%
G = 100
G = 10
1k⍀
0.1%
G = 100
10k⍀
1%
1k⍀
10T
+VS
–
10k⍀
1%
VOUT
AD621
+
–VS
TPC 28. Settling Time Test Circuit
0PW 0 VZR 0
100
90
100V
2V
10
0%
0 WFM
20 WFM AQR WARNING
TPC 26. Gain Nonlinearity, G = 100, RL = 10 kΩ,
CL = 0 pF. Vertical Scale: 100 µV/Div = 100 ppm/Div
Horizontal Scale: 2 Volts/Div
REV. B
–9–