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5. Pinning information
5.1 Pinning
HEF4081B
Quad 2-input AND gate
Fig 3. Pin configuration
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966
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DDJ
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
VSS
VDD
Pin description
Pin
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
14
6. Functional description
Table 3. Function table[1]
Input
nA
nB
L
L
L
H
H
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
Description
input
input
output
ground (0 V)
supply voltage
Output
nY
L
L
L
H
HEF4081B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 15 December 2015
© Nexperia B.V. 2017. All rights reserved
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