TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL CONTROL MODE)
TLL
ALE
TLC
TRW
TCL
RD
WR
AD0-AD7
TLA
TAL
ADDRESS
TRD
TRDF
READ DATA
CS
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
TLC
ADDRESS
TWW
TDW
TWD
WRITE DATA
READ TIMING DIAGRAM (SERIAL CONTROL MODE)
T1 T2
EXCLK
RD
A0-A2
TRCK
TAR
TRA
ADDRESS
DATA
TRD
TCKDR
D0
D1
D2
D3
D4
TRDF
D5
D6
D7
WRITE TIMING DIAGRAM (SERIAL CONTROL MODE)
T2
EXCLK
T1
WR
A0-A2
DATA
TDCK
D0
D1
D2
D3
D4
TCKW
TWW
TAW
TWA
ADDRESS
TCKDW
D5
D6
D7
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© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1