ISP1583ET データシートの表示（PDF） - NXP Semiconductors.
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ISP1583ET Datasheet PDF : 100 Pages
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NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Table 35. Endpoint Index register: bit description
Bit
Symbol
Description
7 to 6 -
reserved
5
EP0SETUP Endpoint 0 Setup: Selects the SETUP buffer for endpoint 0.
0 — Data buffer
1 — SETUP buffer
Must be logic 0 for access to endpoints other than set-up token buffer.
4 to 1
ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of
buffer length, buffer status, control function, data port, endpoint type
and MaxPacketSize.
0
DIR
Direction: Sets the target endpoint as IN or OUT.
0 — Target endpoint refers to OUT (RX) FIFO
1 — Target endpoint refers to IN (TX) FIFO
Table 36. Addressing of endpoint buffers
Buffer name
EP0SETUP
ENDPIDX
DIR
SETUP
1
00h
0
Control OUT
0
00h
0
Control IN
0
00h
1
Data OUT
0
0Xh
0
Data IN
0
0Xh
1
9.3.2 Control Function register (address: 28h)
The Control Function register performs the buffer management on endpoints. It consists
of 1 byte, and the bit configuration is given in Table 37. Register bits can stall, clear or
validate any enabled endpoint. Before accessing this register, the Endpoint Index register
must first be written to specify the target endpoint.
Table 37. Control Function register: bit allocation
Bit
7
6
5
Symbol
reserved
Reset
-
-
-
Bus reset
-
-
-
Access
-
-
-
4
CLBUF
0
0
R/W
3
VENDP
0
0
R/W
2
DSEN
0
0
W
1
STATUS
0
0
R/W
0
STALL
0
0
R/W
ISP1583_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
39 of 99
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