ISP1583ET データシートの表示（PDF） - NXP Semiconductors.
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ISP1583ET Datasheet PDF : 100 Pages
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NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9. Register description
Table 21. Register overview
Name
Destination
Initialization registers
Address
device
Mode
device
Interrupt Configuration device
OTG
device
Interrupt Enable
device
Data flow registers
Endpoint Index
endpoints
Control Function
endpoint
Data Port
endpoint
Buffer Length
endpoint
Buffer Status
endpoint
Endpoint MaxPacketSize endpoint
Endpoint Type
endpoint
DMA registers
DMA Command
DMA controller
DMA Transfer Counter DMA controller
DMA Configuration
DMA controller
DMA Hardware
DMA controller
Address Description
Size Reference
(bytes)
00h
USB device address and enable
1
0Ch
power-down options, global interrupt 2
enable, SoftConnect
10h
interrupt sources, trigger mode,
1
output polarity
12h
OTG implementation
1
14h
interrupt source enabling
4
Section 9.2.1
on page 31
Section 9.2.2
on page 31
Section 9.2.3
on page 33
Section 9.2.4
on page 34
Section 9.2.5
on page 36
2Ch
endpoint selection, data flow direction 1
28h
endpoint buffer management
1
20h
data access to endpoint FIFO
2
1Ch
packet size counter
2
1Eh
buffer status for each endpoint
1
04h
maximum packet size
2
08h
selects endpoint type: isochronous, 2
bulk or interrupt
Section 9.3.1
on page 38
Section 9.3.2
on page 39
Section 9.3.3
on page 40
Section 9.3.4
on page 41
Section 9.3.5
on page 42
Section 9.3.6
on page 43
Section 9.3.7
on page 44
30h
controls all DMA transfers
1
34h
sets byte count for DMA transfer
4
38h
byte 0: sets GDMA configuration
1
(counter enable, data strobing, bus
width)
39h
byte 1: sets ATA configuration (IORDY 1
enable, mode selection: ATA, MDMA,
PIO)
3Ch
endian type, master or slave
1
selection, signal polarity for DACK,
DREQ, DIOW, DIOR, EOT
Section 9.4.1
on page 47
Section 9.4.2
on page 49
Section 9.4.3
on page 50
Section 9.4.4
on page 52
ISP1583_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
29 of 99
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