N25Q128A13BF840F データシートの表示（PDF） - Numonyx -> Micron
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N25Q128A13BF840F
Numonyx -> Micron
N25Q128A13BF840F Datasheet PDF : 180 Pages
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N25Q128
128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,
XiP enabled, serial flash memory with 108 MHz SPI bus interface
Features
SPI-compatible serial bus interface
108 MHz (maximum) clock frequency
2.7 V to 3.6 V single supply voltage
Supports legacy SPI protocol and new Quad
I/O or Dual I/O SPI protocol
Quad/Dual I/O instructions resulting in an
equivalent clock frequency up to 432 MHz:
XIP mode for all three protocols
– Configurable via volatile or non-volatile
registers (enabling the memory to work in
XiP mode directly after power on)
Program/Erase suspend instructions
Continuous read of entire memory via single
instruction:
– Fast Read
– Quad or Dual Output Fast Read
– Quad or Dual I/O Fast Read
Flexible to fit application:
– Configurable number of dummy cycles
– Output buffer configurable
– Fast POR instruction to speed up power on
phase
– Reset function available upon customer
request
64-byte user-lockable, one-time programmable
(OTP) area
Erase capability
– Subsector (4-Kbyte) granularity in the 8
boot sectors (bottom or top parts).
– Sector (64-Kbyte) granularity
Write protections
– Software write protection applicable to
every 64-Kbyte sector (volatile lock bit)
– Hardware write protection: protected area
size defined by five non-volatile bits (BP0,
BP1, BP2, BP3 and TB bit)
VDFPN8 (F8)
8 × 6 mm (MLP8)
SO16 (SF)
300 mils width
TBGA24 (12)
6 x 8 mm
– Additional smart protections available upon
customer request
Electronic signature
– JEDEC standard two-byte signature
(BA18h)
– Additional 2 Extended Device ID (EDID)
bytes to identify device factory options
– Unique ID code (UID) with 14 bytes read-
only, available upon customer request
More than 100,000 program/erase cycles per
sector
More than 20 years data retention
Packages
– RoHS compliant
February 2010
Rev 1.0
1/180
www.numonyx.com
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