QL7100-6PQ208C データシートの表示（PDF） - QuickLogic Corporation

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QL7100-6PQ208C

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

EclipsePlus Family Data Sheet Rev. A

Electrical Specifications

AC Characteristics*

*(at VCC = 2.5 V, TA = 25° C, Typical Corner, Speed Grade = -7 (K = 1.00))

The AC Specifications are provided from Table 6 to Table 14. Logic Cell diagrams and waveforms are

provided from Figure 5 to Figure 18.

Figure 5: EclipsePlus Logic Cell

Symbol

tPD

tSU

tHL

tCO

tCWHI

tCWLO

tSET

Table 6: Logic Cells

Parameter

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to

output

Setup time: time the synchronous input of the flip flop must be stable before the

active clock edge

Hold time: time the synchronous input of the flip flop must be stable after the active

clock edge

Clock to out delay: the amount of time taken by the flip flop to output after the active

clock edge.

Clock High Time: required minimum time the clock stays high

Clock Low Time: required minimum time that the clock stays low

Set Delay: time between when the flip flop is ”set” (high)

and when the output is consequently “set” (high)

Value (ns)

Min. Max.

0.205 1.01

0.231

-

0

-

-

0.427

0.46

-

0.46

-

-

0.585

© 2006 QuickLogic Corporation

www.quicklogic.com

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