QL7100-6PQ208M データシートの表示（PDF） - QuickLogic Corporation

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QL7100-6PQ208M

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

EclipsePlus Family Data Sheet

• • • • • • Combining Performance, Density, and Embedded RAM

Device Highlights

Flexible Programmable Logic

• 0.25 µm five layer metal CMOS process

• 2.5 V VCC, 2.5/3.3 V drive capable I/O

• Up to 4,032 logic cells

• Up to 583,008 system gates

• Up to 347 I/O pins

Embedded Dual-Port SRAM

• Up to thirty-six 2,304-bit dual-port high

performance SRAM blocks

• Up to 82,900 RAM bits

• RAM/ROM/FIFO wizard for automatic

configuration

• Configurable and cascadable

Programmable I/O

• High performance enhanced I/O (EIO)—

less than 3 ns Tco

• Programmable slew rate control

• Programmable I/O standards:

 LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

 Eight independent I/O banks

 Three register configurations: input, output,

and output enable

Advanced Clock Network

• Nine global clock networks:

 One dedicated

 Eight programmable

• 20 quad-net networks—five per quadrant

• 16 I/O controls—two per I/O bank

• Four phase locked loops

Embedded Computational Units

ECUs provide integrated multiply, add, and

accumulate functions.

Figure 1: EclipsePlus Block Diagram

PLL

Memory - Dual Port RAM

PLL

Embedded Computational Units

High Speed Logic Cells

583K Gates

PLL

Memory - Dual Port RAM

PLL

© 2006 QuickLogic Corporation

www.quicklogic.com

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