FM3104 データシートの表示（PDF） - Ramtron International Corporation

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FM3104

Integrated Processor Companion with Memory

Ramtron International Corporation 

FM3104/16/64/256

AC Test Conditions

Input Pulse Levels

Input rise and fall times

Input and output timing levels

0.1 VDD to 0.9 VDD

10 ns

0.5 VDD

Diagram Notes

All start and stop timing parameters apply to both read and write

cycles. Clock specifications are identical for read and write cycles.

Write timing parameters apply to slave address, word address, and

write data bits. Functional relationships are illustrated in the relevant

data sheet sections. These diagrams illustrate the timing parameters

only.

Equivalent AC Load Circuit

5.5V

Output

1700 Ω

100 pF

Read Bus Timing

SCL

tR

tHIGH

` tF

tLOW

tSP

tSP

tSU:SDA

tBUF

SDA

1/fSCL

tHD:DAT

tSU:DAT

Start

Stop Start

tAA

tDH

Acknowledge

Write Bus Timing

SCL

SDA

tSU:STO

tHD:DAT

tHD:STA

tSU:DAT

tAA

/RST Timing

Start

Stop Start

Acknowledge

VDD

tVF

VTP

tVR

VRST

tRNR

tR P U

RST

Rev 0.2

May 2003

Page 20 of 22

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