MT46V16M16BG-75 データシートの表示（PDF） - Micron Technology

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MT46V16M16BG-75

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

256Mb: x4, x8, x16

DDR SDRAM

Figure 42: Data Output Timing – tAC and tDQSCK

T07

T1

CK#

CK

tLZ (MIN)

T2

T2n

T3

T3n

T4

T4n T5

T5n

T6

tDQSCK1 (MAX)

tDQSCK1 (MIN)

tDQSCK1 (MAX)tHZ(MAX)

tDQSCK1 (MIN)

DQS, or LDQS/UDQS2

tRPRE

tRPST

DQ (Last data valid)

DQ (First data valid)

All DQ values, collectively3

tLZ (MIN)

T2 T2n T3 T3n T4 T4n T5 T5n

T2

T2n

T3

T3n T4

T4n

T5 T5n

T2

T2n

T3

T3n T4

T4n T5

T5n

tAC4 (MIN)

tAC4 (MAX)

tHZ (MAX)

NOTE:

1. tDQSCK is the DQS output window relative to CK and is the “long-term” component of DQS skew.

2. DQ transitioning after DQS transition define tDQSQ window.

3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

4. tAC is the DQ output window relative to CK, and is the “long-term” component of DQ skew.

5. tLZ (MIN) and tAC (MIN) are the first valid signal transition.

6. tHZ (MAX),and tAC (MAX) are the latest valid signal transition.

7. READ command with CL = 2 issued at T0.

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

67

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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