PTN3392BS データシートの表示（PDF） - NXP Semiconductors.

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PTN3392BS

2-lane DisplayPort to VGA adapter IC

NXP Semiconductors. 

NXP Semiconductors

5. Functional diagram

PTN3392

2-lane DisplayPort to VGA adapter IC

lane 0

PTN3392

RX PHY

ANALOG

SUBSYSTEM

DIFF CDR,

RCV S2P

lane 1

Vbias

DIFF CDR,

RCV S2P

AUX

Vbias

RCV

DRV

Vbias

Fig 1. Functional diagram

RX PHY DIGITAL

ISOCHRONOUS LINK

R[7:0]

TIME

CONV.

MAIN G[7:0]

STREAM

B[7:0]

TIMING RECOVERY

H, V

sync

VIDEO DAC SUBSYSTEM

DAC

DAC

DAC

VGA

OUTPUT

DPCD

REGISTERS

CONTROL

FLASH MCU

R

G

B

HSYNC

VSYNC

MANCHESTER

CODEC

AUX COMMAND

LEVEL MODULE

RX ACLI

RX DIGITAL SUBSYSTEM

I2C-BUS

MASTER

SCL

SDA

002aae032

PTN3392

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 5 June 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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