74HC4046APW データシートの表示（PDF） - NXP Semiconductors.

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74HC4046APW

Phase-locked loop with VCO

NXP Semiconductors. 

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Symbol Parameter

Conditions

ΔICC

CI

additional

supply current

input

capacitance

INH; VI = VCC - 2.1 V; COMP_IN and

SIG_IN at VCC; VCO_IN at GND; II at pins

COMP_IN and SIGN_IN to be excluded

VCC = 4.5 V to 5.5 V

INH

25 °C

-40 °C to -40 °C to Unit

+85 °C +125 °C

Min Typ Max Min Max Min Max

- 100 360 - 450 - 490 μA

- 3.5 -

-

-

-

- pF

[1] The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ.

11.3. Graphs

II

(µA)

VI

800

RI

(kΩ)

600

aaa-020213

VCC = 3.0 V

400

self-bias operating point

0

VI (V)

aaa-020212

Fig. 13. Typical input resistance curve at SIG_IN and

COMP_IN

+5

II

(µA)

0

3.0 V

4.5 V

6.0 V

aaa-020214

VCC = 6.0 V

4.5 V

3.0 V

-5

1/2 VCC -0.25

1/2 VCC

1/2 VCC +0.25

VI (V)

Fig. 15. Input current at SIG_IN, COMP_IN with

ΔVI = 0.5 V at self-bias point

200

4.5 V

0

1/2 VCC -0.25

1/2 VCC

6.0 V

1/2 VCC +0.25

VI (V)

Fig. 14. Input resistance at SIG_IN, COMP_IN with

ΔVI = 0.5 V at self-bias point

+60

Voffset

(mV)

aaa-020215

+40

VCC = 3.0 V

+20

0

4.5 V

-20

6.0 V

-40

1/2 VCC -2

1/2 VCC

1/2 VCC +2

VVCO_IN (V)

___ Rs = 50 kΩ

- - - Rs = 300 kΩ

Fig. 16. Offset voltage at demodulator output as

a function of VVCO_IN and Rs

74HC_HCT4046A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 6 August 2019

© Nexperia B.V. 2019. All rights reserved

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