ADAU1451WBCPZ-RL データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
ADAU1451WBCPZ-RL Datasheet PDF : 180 Pages
| |||
ADAU1452/ADAU1451/ADAU1450
Data Sheet
Serial Ports
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, unless otherwise noted. BCLK in Table 8 refers to
BCLK_OUT3 to BCLK_OUT0 and BCLK_IN3 to BCLK_IN0. LRCLK refers to LRCLK_OUT3 to LRCLK_OUT0 and LRCLK_IN3 to
LRCKL_IN0.
Table 8.
Parameter
SERIAL PORT
fLRCLK
tLRCLK
fBCLK
tBCLK
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tTS
tSODS
Min
5.21
40.7
10
14.5
20
5
5
5
tSODM
tTM
Max Unit Description
192
kHz LRCLK frequency
µs LRCLK period
24.576 MHz BCLK frequency, sample rate ranging from 6 kHz to 192 kHz
ns BCLK period
ns BCLK low pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns
ns BCLK high pulse width, slave mode; BCLK frequency = 24.576 MHz; BCLK period = 40.6 ns
ns LRCLK setup to BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz
ns LRCLK hold from BCLK_INx input rising edge, slave mode; LRCLK frequency = 192 kHz
ns SDATA_INx setup to BCLK_INx input rising edge
ns SDATA_INx hold from BCLK_INx input rising edge
10
ns BCLK_OUTx output falling edge to LRCLK_OUTx output timing skew, slave
35
ns SDATA_OUTx delay in slave mode from BCLK_OUTx output falling edge; serial outputs function in slave mode
at all valid sample rates, provided that the external circuit design provides sufficient electrical signal integrity
10
ns SDATA_OUTx delay in master mode from BCLK_OUTx output falling edge
5
ns BCLK falling edge to LRCLK timing skew, master
BCLK_INx
LRCLK_INx
SDATA_INx
LEFT JUSTIFIED MODE
(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b01)
SDATA_INx
I2S MODE
(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b00)
SDATA_INx
RIGHT JUSTIFIED MODES
(SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b10
OR
SERIAL_BYTE_x_0[4:3], (DATA_FMT) = 0b11)
tBIH
tBIL
tLIS
tBCLK
tLRCLK
tSIS
MSB
tSIH
MSB – 1
tSIS
MSB
tSIH
tSIS
MSB
tSIH
Figure 5. Serial Input Port Timing Specifications
tLIH
tTM
tSIS
LSB
tSIH
tBIH
tBCLK
tTS
BCLK_OUTx
tBIL
LRCLK_OUTx
SDATA_OUTx
LEFT JUSTIFIED MODE
(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b01)
ttSSOODDMS
MSB
MSB – 1
tLRCLK
SDATA_OUTx
I2S MODE
(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b00)
ttSSOODDMS
MSB
SDATA_OUTx
RIGHT JUSTIFIED MODES
(SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b10
OR
SERIAL_BYTE_x_0 [4:3] (DATA_FMT) = 0b11)
ttSSOODDSM
MSB
LSB
Figure 6. Serial Output Port Timing Specifications
Rev. C | Page 10 of 180
Share Link: 