AD7892 データシートの表示（PDF） - Analog Devices
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AD7892 Datasheet PDF : 14 Pages
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AD7892
TIMING CHARACTERISTICS1, 2 (VDD = +5 V ؎ 5%, AGND = DGND = 0 V, REF IN = +2.5 V)
Parameter
A, B
Versions
S
Version
Unit
Test Conditions/Comments
tCONV
tACQ
Parallel Interface
t1
t2
t3
t4
t5
t63
t74
t8
t9
Serial Interface
t10
t113
t12
t13
t143
t153
t16
t174
t17A4
1.47
1.6
200
400
35
60
0
0
35
35
5
30
0
200
30
25
25
25
5
25
20
0
30
0
30
µs max
Conversion Time for AD7892-3
1.68
µs max
Conversion Time for AD7892-1, AD7892-2
ns min
Acquisition Time for AD7892-3
320
ns min
Acquisition Time for AD7892-1, AD7892-2
45
ns min
CONVST Pulsewidth
60
ns min
EOC Pulsewidth
0
ns min
EOC Falling Edge to CS Falling Edge Setup Time
0
ns min
CS to RD Setup Time
45
ns min
Read Pulsewidth
40
ns max
Data Access Time After Falling Edge of RD
5
ns min
Bus Relinquish Time After Rising Edge of RD
40
ns max
0
ns min
CS to RD Hold Time
200
ns min
RD to CONVST Setup Time
35
ns min
RFS Low to SCLK Falling Edge Setup Time
30
ns max
RFS Low to Data Valid Delay
25
ns min
SCLK High Pulsewidth
25
ns min
SCLK Low Pulsewidth
5
ns min
SCLK Rising Edge to Data Valid Hold Time
30
ns max
SCLK Rising Edge to Data Valid Delay
30
ns min
RFS to SCLK Falling Edge Hold Time
0
ns min
Bus Relinquish Time after Rising Edge of RFS
30
ns max
0
ns min
Bus Relinquish Time after Rising Edge of SCLK
30
ns max
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2See Figures 2 and 3.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN 50pF
+1.6V
200A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
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