LFSC3GA40E-5FFN1020I データシートの表示（PDF） - Lattice Semiconductor
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LFSC3GA40E-5FFN1020I Datasheet PDF : 237 Pages
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Lattice Semiconductor
Revision History
LatticeSC/M Family Data Sheet
Date
March 2007
(cont.)
August 2007
Version
01.5
(cont.)
01.6
Section
Change Summary
DC and Switching Updated LatticeSC Internal Timing Parameters with ispLEVER 6.1 SP1
Characteristics (cont.) results.
Updated tFDEL and tCDEL specifications.
Updated LatticeSC Family Timing Adders with ispLEVER 6.1 SP1
results.
Updated PLL specifications to expand frequency range down to 2 MHz
and break out jitter for the different ranges.
Added footnote to sysCLOCK PLL Timing table specifying the condi-
tions for the jitter measurements.
Added tDLL specification to sysCLOCK DLL Timing table.
Added footnote to sysCLOCK DLL Timing table specifying the condi-
tions for the jitter measurements.
Added sysCONFIG Master Parallel Configuration Mode and sysCON-
FIG SPI Port to LatticeSC sysCONFIG Port Timing table.
Pin Information Updated Pin Information Summary with SC40 information.
Updated LFSC25 Logic Signal Connections: FF1020 with SC40 infor-
mation.
Updated LFSC80 Logic Signal Connections: FC1152 with SC40 infor-
mation.
General
Changed references of "HDC" to "HDC/SI".
Changed references of "LDCN" to "LDCN/SCS".
Changed references of "BUSYN/RCLK" to "BUSYN/RCLK/SCK".
Changed references of "RDCFGN" to "TSALLN".
Changed references of "TDO/RDDATA" to "TDO".
Architecture
Updated text in Ripple Mode section.
Added information to Global Set/Reset.
Added information for Spread Spectrum Clocking
Modified information for PLL/DLL Cascading. DLL to PLL is now sup-
ported.
Modified AIL Block text and figure.
Modified Figure 2-20 DDR/Shift Register Block.
Added Information to Hot Socketing.
Added new information for I/O Architecture Rules.
Added information to SERDES Power Supply Sequencing Require-
ments.
DC and Switching Added footnote to Hot Socketing Specifications table.
Characteristics
Modified Initialization and Standby Supply Current table.
Modified GSR Timing table.
Modified sysCLOCK DLL Timing table to include IDUTY.
Deleted Readback Timing information from sysCONFIG Port Timing
table.
Modified data in External Switching Characteristics table.
Pin Information
Added information to the Signal Descriptions table for HDC/SI, LDCN/
SCS.
Added footnote to Signal Descriptions table.
Modified Description for signal BUSYN/RCLK/SCK.
Modified data in Pin Information Summary and device-specific Pinout
Information tables.
7-4
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