73S8010R-IMR/F データシートの表示（PDF） - Maxim Integrated

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73S8010R-IMR/F

Low Cost Smart Card Interface

Maxim Integrated 

73S8010R Data Sheet

DS_8010R_022

Symbol Parameter

Condition

Min Nom Max Unit

Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,

AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC.

VOH

Output level, high (I/O, IOH = 0 µA

AUX1, AUX2)

IOH = -40 µA

0.9 * VCC –

VCC+0.1

V

0.75 * VCC –

VCC+0.1

V

VOH

Output level, high

(I/OUC, AUX1UC,

AUX2UC)

IOH = 0 µA

IOH = -40 µA

0.9 * VCC –

VDD+0.1

V

0.75 * VCC –

VDD+0.1

V

VOL

Output level, low

IOL = 1 mA

VIH

Input level, high (I/O,

AUX1, AUX2)

–

–

0.3

V

1.8

– VCC+0.30 V

VIH

Input level, high (I/OUC,

AUX1UC, AUX2UC)

1.8

– VCC+0.30 V

VIL

VINACT

ILEAK

Input level, low

Output voltage when

outside of session

Input leakage

IOL = 0

IOL = 1 mA

VIH = VCC

-0.3

–

0.8

V

–

–

0.1

V

–

–

0.3

V

–

–

10

µA

IIL

ISHORTL

Input current, low

Short circuit output

current

VIL = 0

For output low, shorted

to VCC through 33 Ω

–

–

0.65

mA

–

–

15

mA

ISHORTH Short circuit output

For output high, shorted

–

–

15

mA

current

to ground through 33 Ω

tR, tF

Output rise time, fall

For I/O, AUX1, AUX2,

–

time

CL = 80 pF, 10% to 90%.

For I/OUC, AUX1UC,

AUX2UC, CL=50 pF,

10% to 90%.

–

100

ns

tIR, tIF

Input rise, fall times

–

–

1

µs

RPU

Internal pull-up resistor Output stable for >200 ns

8

11

14

kΩ

FDMAX Maximum data rate

–

–

1

MHz

TFDIO

Delay, I/O to I/OUC,

Falling edge from master

60

100

200

ns

I/OUC to I/O, AUX1 to to slave measured at

AUX1UC, AUX1UC to 50% point

AUX1, AUX2 to AUX2UC,

AUX2UC to AUX2

TRDIO

Delay, I/O to I/OUC,

Rising edge from master

–

25

90

ns

I/OUC to I/O, AUX1 to

to slave measured at

AUX1UC, AUX1UC to 50% point

AUX1, AUX2 to AUX2UC,

AUX2UC to AUX2

CIN

Input capacitance

–

–

10

pF

10

Rev. 1.6

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