HEF4043BT-Q100J データシートの表示（PDF） - NXP Semiconductors.
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HEF4043BT-Q100J Datasheet PDF : 15 Pages
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NXP Semiconductors
HEF4043B-Q100
Quad R/S latch with 3-state outputs
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration
+()%4
4
4
5
6
2(
6
5
966
9''
5
6
QF
6
5
4
4
DDD
6.2 Pin description
Table 2. Pin description
Symbol
Pin
1Q to 4Q
2, 9, 10, 1
1R to 4R
3, 7, 11, 15
1S to 4S
4, 6, 12, 14
OE
5
VSS
8
n.c.
13
VDD
16
7. Functional description
Description
3-state buffered latch output
reset input (active HIGH)
set input (active HIGH)
common output enable input
ground supply voltage
not connected
supply voltage
Table 3. Function table[1]
Inputs
OE
nS
nR
L
X
X
H
L
H
H
H
X
H
L
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
Output
nQ
Z
L
H
latched
HEF4043B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
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