SAF7741 データシートの表示（PDF） - NXP Semiconductors.

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SAF7741

Car radio Digital Signal Processor (DSP)

NXP Semiconductors. 

NXP Semiconductors

SAF7741HV

Dual IF car radio and audio DSP (N1F)

DR_WS

DR_BCK

DR_I_DAT LSB MSB

DR_Q_DAT LSB MSB

SAMPLE n−1

Fig 14. Digital radio I2S output format

LSB MSB

LSB MSB

SAMPLE n

LSB MSB

LSB MSB

7.1.4 RGP DAC

RGP digital-to-analog conversion is performed by a 10-bit DAC with a buffered output.

This is part of the radio subsystem and can be used for various functions linked to the

radio domain.

A double buffered interface is located between the DSP and the RGP DAC. The buffer is

2 × 8 words in length, which means that data with a maximum sample rate of 8 Fs (i.e.

325 kHz) can be transferred to the output when the DSP is running at 1 Fs (i.e.

40.625 kHz).

7.1.4.1 TEF6730 tuner compatibility

In TEF6730 tuner compatibility mode the general-purpose DAC can be used for

controlling the PIN diode in front of the tuner. In addition to its digital AGC function this

operates as second-level gain correction for the IFADC.

7.1.5 Radio Data System demodulator/decoder

7.1.5.1 General description

There are two Radio Data System (RDS) demodulation and decoder systems available on

the SAF7741HV. The description below applies to each of them.

The RDS function recovers the additional and inaudible RDS information transmitted by

FM radio broadcasting. The operational functions of the demodulator and the decoder are

in accordance with EBU specification EN50067.

The function processes the RDS signal frequency-multiplexed within the stereo MultiPleX

(MPX) signal to recover the information transmitted over the RDS data channel. This

processing consists of band-pass filtering, demodulation and RDS/ Radio Broadcast Data

System (RBDS) decoding. The RDS band-pass filter discards the audio content from the

input signal and reduces the bandwidth.

The RDS demodulator regenerates the raw RDS bitstream (bit rate = 1187.5 Hz) from the

modulated RDS signal. Connection to the RDS/RBDS decoder is by means of the DSP

flags (see Figure 15).

Under I2C control via bit rds_clkin an internal buffer can be used to read out the raw RDS

stream in bursts of 16 bits. With the I2C bit rds_clkout the RDS clock can be either

enabled or switched off.

SAF7741_5

Objective data sheet

Rev. 05 — 09 May 2008

© NXP B.V. 2008. All rights reserved.

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