MAX1536ETI-T データシートの表示（PDF） - Maxim Integrated

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MAX1536ETI-T

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step Down Regulator with Dynamic Output Voltage Control

Maxim Integrated 

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-

Down Regulator with Dynamic Output Voltage Control

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA = 0°C to +85°C, unless otherwise noted. Typical

values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Shutdown Supply Currents

ICC + IIN

IIN

ILX

SHDN = AGND; current into VCC and IN;

LX = 0 or +3.3V

SHDN = AGND; current into IN; LX = 0

SHDN = AGND; current into LX; LX = +3.3V

0.2

20

µA

0.2

20

0.1

20

REFERENCE

REF Voltage

VREF VCC = VIN = +3.0V to +5.5V

1.985 2.000 2.015

V

REF Load Regulation

REFIN Input Voltage Range

REFIN Input Bias Current

IREF = -1µA to +50µA

VREFIN VCC = VIN = +3.0V to +5.5V, VCC > VREFIN + 1.35V

0.7

IREFIN VREFIN = 1.5V, VFB = 1.01 × VREFIN

-50

10

mV

2.0

V

+50

nA

FAULT DETECTION

Thermal Shutdown

TSHDN Rising, hysteresis = 15°C

165

°C

Undervoltage Lockout

Threshold

PGOOD Lower Trip Threshold

VCC and VIN rising, hysteresis 60mV typical

2.4

2.6

2.8

VCC - VREFIN, VCC rising, hysteresis 60mV typical

0.9 1.35

V

VCC - VFB, VCC rising, hysteresis 60mV typical

0.9 1.35

No load, falling edge, hysteresis = 1% (Note 4)

-12.5 -10 -8.0

%

PGOOD Upper Trip Threshold

No load, rising edge, hysteresis = 1% (Note 4)

+8.0 +10 +12.5 %

PGOOD Propagation Delay

tPGOOD FB forced 2% beyond PGOOD trip threshold

5

µs

PGOOD Output Low Voltage

PGOOD Leakage Current

ISINK = 1mA

High-impedance state, forced to +5.5V

0.1

V

1

µA

FBLANK = VCC

112 150 188

Fault Blanking Time

tFBLANK FBLANK = open or AGND

75

100 125

µs

FBLANK = REF

37

50

63

INPUTS AND OUTPUTS

Logic Input Threshold

V SHDN,

V SKIP,

VGATE

SHDN, SKIP, GATE, VIN = VCC = +3.3V,

rising edge, hysteresis = 100mV

SHDN, SKIP, GATE, VIN = VCC = +5.0V,

rising edge, hysteresis = 100mV

0.9

1.3

1.6

V

1.15 1.55 1.95

Logic Input Current

SHDN, SKIP, GATE

-0.5

+0.5 µA

FBLANK Logic Thresholds

VFBLANK

FBLANK = VCC

FBLANK = REF

FBLANK = open

VCC - 0.2

1.8

0.8

2.2

V

1.2

FBLANK = AGND

0.2

FBLANK Input Current

OD On-Resistance

OD Leakage Current

OD On-Resistance

OD Leakage Current

IFBLANK

ROD

R OD

FBLANK forced to AGND or VCC

GATE = VCC

GATE = AGND, VOD = +5.5V

GATE = AGND

GATE = VCC, VOD = +5.5V

-5

+5

µA

10

25

Ω

-50

+50

nA

10

25

Ω

-50

+50

nA

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