ADUC7033 データシートの表示（PDF） - Analog Devices

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ADUC7033

Integrated, Precision Battery Sensor for Automotive

Analog Devices 

ADuC7033

LIN (LOCAL INTERCONNECT NETWORK) INTERFACE

The ADuC7033 features high voltage physical interfaces

between the ARM7 MCU core and an external LIN bus. The

LIN interface operates as a slave only interface, operating from

1 kBaud to 20 kBaud, and it is compatible with the LIN 2.0

standard. The pull-up resistor required for a slave node is on-

chip, reducing the need for external circuitry. The LIN protocol

is emulated using the on-chip UART, an IRQ, a dedicated LIN

timer, and the high voltage transceiver (also incorporated on-

chip) as shown in Figure 4. The LIN is clocked from the low

power oscillator for the break timer, and a 5 MHz output from

the PLL is used for the synchronous byte timing.

LIN MMR DESCRIPTION

The LIN hardware synchronization (LHS) functionality is

controlled through five MMRs. The function of each MMR is as

follows:

Table 92. LIN MMR Descriptions

MMR

Name

Description

LHSSTA

LHS Status Register. This MMR contains information

flags that describe the current status on the

interface.

LHSCON0 LHS Control Register 0. This MMR controls the

configuration of the LHS timer.

LHSCON1

LHS Start and Stop Edge Control Register. Dictates

which edge of the LIN synchronization byte the

LHS starts/stops counting.

LHSVAL0 LHS Synchronization 16-Bit Timer. Controlled by

LHSCON0.

LHSVAL1 LHS Break Timer Register.

LHS INTERRUPT

IRQEN[7]

5MHz

ADuC7033

LHS

HARDWARE

LHSVAL0

LHS

INTERRUPT

LOGIC

FOUR LIN

INTERRUPT

SOURCES

BREAK LHSSTA[0]

START LHSSTA[1]

STOP LHSSTA[2]

BREAK

ERROR LHSSTA[4]

VDD

131kHz

LHSVAL1

RxD ENABLE

LHSCON0[8]

INPUT

VOLTAGE

THRESHOLD

REFERENCE

LIN ENABLE

(INTERNAL

PULL-UP)

HVCFG0[5]

EXTERNAL

LIN PIN

GPIO_12

GP2DAT[29]

AND

GP2DAT[21]

RxD

ADuC7033

UART

TxD

GPIO12

FUNCTION

SELECT

GP2CON[20]

LIN MODE

HVCFG0[1:0]

OVER

VOLTAGE SCR

PROTECTION

OUTPUT

DISABLE

BPF

SHORT-CIRCUIT

CONTROL

HVCFG1[2]

INTERNAL

SHORT-CIRCUIT

SENSE

RESISTOR

INTERNAL

SHORT-CIRCUIT

TRIP REFERENCE

IO_VSS

Figure 45. LIN I/O, Block Diagram

VDD

MASTER ECU

PROTECTION

DIODE

MASTER ECU

PULL-UP

CLOAD

Rev. B | Page 121 of 140

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