AD7091R-8BRUZ データシートの表示（PDF） - Analog Devices
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AD7091R-8BRUZ Datasheet PDF : 42 Pages
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AD7091R-2/AD7091R-4/AD7091R-8
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
CS 1
RESET 2
16 VDRIVE
15 CONVST
VDD 3
14 SCLK
REGCAP 4 AD7091R-2 13 SDO
REFIN/REFOUT 5
TOP VIEW
(Not to Scale) 12 SDI
GND 6
11 GND
MUXOUT 7
VIN0 8
10 ADCIN
9 VIN1
Figure 5. 2-Channel, 16-Lead TSSOP Pin Configuration
VDD 1
REGCAP 2
REFIN/REFOUT 3
GND 4
AD7091R-2
TOP VIEW
(Not to Scale)
12 SCLK
11 SDO
10 SDI
9 GND
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
Figure 6. 2-Channel, 16-Lead LFCSP Pin Configuration
Table 5. 2-Channel, 16-Lead LFCSP and 16-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP Mnemonic Description
1
15
CS
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on the SPI.
2
16
RESET
Reset. Logic input.
3
1
VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
4
2
REGCAP
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
5
3
REFIN/REFOUT Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an externally
applied reference is 1.0 V to VDD.
6, 11
4, 9 GND
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-2.
7
5
MUXOUT
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
8
6
VIN0
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9
7
VIN1
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
10
8
ADCIN
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network
to the MUXOUT pin.
12
10
SDI
Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSBs first.
13
11
SDO
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The
bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are required to access the
data. The data is provided MSB first.
14
12
SCLK
Serial Clock. This pin acts as the serial clock input.
15
13
CONVST
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-
and-hold mode into hold mode and initiates a conversion.
16
14
VDRIVE
Not
17
applicable
EPAD
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended values are 10 μF
and 0.1 μF. The voltage range on this pin is 1.8 V to 5.25 V and may be different to the voltage range
at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 8 of 42
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