MAX17021EVKIT データシートの表示（PDF） - Maxim Integrated

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MAX17021EVKIT

MAX17021 Evaluation Kit

Maxim Integrated 

MAX17021 Evaluation Kit

Setting the Output Voltage

The MAX17021 has an internal digital-to-analog con-

verter (DAC) that programs the output voltage. The out-

put voltage can be digitally set from 0 to 1.5000V

(Table 2) from the D0–D6 pins. There are two different

ways of setting the output voltage:

1) Drive the external VID0–VID6 inputs (all SW1

positions are off). The output voltage is set by dri-

ving VID0–VID6 with open-drain drivers (pullup

resistors are included on the board) or 3V/5V CMOS

output logic levels.

Table 1. MAX17021 Operating Mode Truth Table

INPUTS

SHDN DPRSTP DPRSLPVR

SW2 SW2

SW2

(1, 10) (5, 6)

(2, 9)

PSI

SW2

(3, 8)

PHASE

OPERATION*

OPERATING MODE

GND

X

Rising X

High High

High High

High Low

High High

Falling X

High

X

X

X

Low

Low

High

High

X

X

X

X

High

Low

X

X

X

X

Disabled

Low-Power Shutdown Mode. DL1 and DL2 are forced low and the

controller is disabled. The supply current drops to 1µA (max).

Multiphase

Pulse Skipping

1/8 RTIME

Slew Rate

Startup/Boot. When SHDN is pulled high, the MAX17021 begins the

startup sequence. The controller enables the PWM controller and

ramps the output voltage up to the boot voltage.

Multiphase

Forced-PWM

Normal RTIME

Slew Rate

Full Power. The no-load output voltage is determined by the selected

VID DAC code (D0–D6, Table 2).

1-Phase

Forced-PWM

Normal RTIME

Slew Rate

Intermediate Power. The no-load output voltage is determined by the

selected VID DAC code (D0–D6, Table 2). When PSI is pulled low, the

MAX17021 immediately disables phase 2. DH2 and DL2 are pulled low.

1-Phase Pulse

Skipping

Normal RTIME

Slew Rate

Deeper Sleep Mode. The no-load output voltage is determined by the

selected VID DAC code (D0–D6, Table 2). When DPRSLPVR is pulled

high, the MAX17021 immediately enters 1-phase pulse-skipping

operation allowing automatic PWM/PFM switchover under light loads.

The PWRGD and CLKEN upper thresholds are blanked during

downward transitions. DH2 and DL2 are pulled low.

1-Phase Pulse

Skipping

1/4 RTIME Slew

Rate

Deeper Sleep Slow Exit Mode. The no-load output voltage is

determined by the selected VID DAC code (D0–D6, Table 2).

When DPRSTP is pulled high while DPRSLPVR is already high, the

MAX17021 remains in one-phase pulse-skipping operation, allowing

automatic PWM/PFM switchover under light loads, but reduces its

slew rate to 1/4 of normal.

Multiphase

Forced-PWM

1/8 RTIME

Slew Rate

Shutdown. When SHDN is pulled low, the MAX17021 immediately

pulls PWRGD and PHASEGD low, CLKEN becomes high impedance,

all enabled phases are activated, and the output voltage is ramped

down to ground. Once the output reaches 0V, the controller enters the

low-power shutdown state.

Disabled

Fault Mode. The fault latch has been set by the MAX17021 UVP or

thermal-shutdown protection, or by the OVP protection. The controller

remains in fault mode until VCC power is cycled or SHDN toggled.

*Multiphase operation = All enabled phases active.

X = Don’t care.

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