PI6C2509-133 データシートの表示（PDF） - Pericom Semiconductor Corporation
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PI6C2509-133
Pericom Semiconductor Corporation
PI6C2509-133 Datasheet PDF : 4 Pages
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PI6C2509-133
Low-Noise, Phase-Locked Loop
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Functional Table
Input Control
X(1)G
Outputs
X(1)Y[0:3] FB_OUT
L
L
CLK_IN
H
Note:
1. X is either 1 or 2
CLK_IN
CLK_IN
Pin Functions
Pin Name Pin No.
CLK_IN
24
FB_IN
13
1G
11
2G
14
FB_OUT
12
1Y[0:4]
2Y[3:0]
3,4,5,8,9
16,17,
20, 21
AVCC
23
AGND
VCC
GND
1
2,10,15,22
6,7,18,19
Type
Description
I
Clock input. CLK_IN allows spread spectrum.
I
Feedback input. FB_IN provides the feedback signal to the internal PLL.
I
Output bank enable. When 1G is LOW, outputs 1Y[0:4] are disabled to
a logic low state. When 1G is HIGH, all outputs 1Y[0:4] are enabled.
I
Output bank enable. When 2G is LOW, outputs 2Y[0:3] are disabled to
a logic low state. When 2G is HIGH, all outputs 2Y[0:3] are enabled.
O
Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an
embedded series-damping resistor of the same value as the clock outputs 1Yx, 2Yx.
O
Clock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
O
Clock outputs. These outputs provide low-skew copies of CLK_IN.
Each output has an embedded series-damping resistor.
Power
Analog power supply. AVCC can be also used to bypass the PLL for
test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK_IN.
is buffered directly to the device outputs.
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply.
Ground Ground.
2
PSXXXX
06/01/99
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