LTC1482 データシートの表示（PDF） - Linear Technology
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LTC1482 Datasheet PDF : 16 Pages
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LTC1482
PIN FUNCTIONS
(DE = 0, DI/SHDN = 0) or to disable the driver while keeping
the receiver alive (DE = 0, DI/SHDN = 1). When the driver
is enabled (DE = 1), DI/SHDN = 0 forces the A output low
and the B output high. DI/SHDN = 1 forces the A output
high and the B output low.
GND (Pin 5): Ground.
A (Pin 6): Driver Output/Receiver Input. The input resis-
tance is typically 22k when the driver is disabled (DE = 0).
When the driver is enabled, the A output follows the logic
level at the DI/SHDN pin.
B (Pin 7): Driver Output/Receiver Input. The input resis-
tance is typically 22k when the driver is disabled (DE = 0).
When the driver is enabled, the B output is inverted from
the logic level at the DI/SHDN pin.
VCC (Pin 8): Positive Supply. 4.75V < VCC < 5.25V. A 0.1µF
bypass capacitor is recommended.
FU CTIO TABLES
Driver Enabled (DE = 1)
DI/SHDN
A
B
0
0
1
1
1
0
X
A Shorted to B
RO
CD
0
0
1
0
1
1
Note 1: DE = 0, DI/SHDN = 0 puts the part in ICC shutdown and the supply
current drawn by the VCC pin drops to 20µA max. The receiver is always
alive except in shutdown.
Note 2: The table is valid regardless of the presence of an external
termination resistor.
Note 3: Although the RO and the driver outputs are three-stated, the A and
B pins each present a 22kΩ receiver input resistance to ground.
Driver Disabled (DE = 0, Notes 1, 2)
DI/SHDN
A–B
0
X (Note 3)
1
VTHCD(MIN) < (A – B) < VTHCD(MAX)
1
A and B are Open
1
A and B are Shorted
1
VTHCD(MIN) ≥ (A – B) ≥ VTHCD(MAX)
and (A – B) ≤ VTHRO(MIN)
1
VTHCD(MIN) ≥ (A – B) ≥ VTHCD(MAX)
and (A – B) ≥ VTHRO(MAX)
X = Don’t Care
Z = High Impedance
RO
CD
Z 1 (Internal Pull-Up)
1
1
1
1
1
1
0
0
1
0
TEST CIRCUITS
A
R
VOD
B
R
1482 F01
VOC
375Ω
A
VOD3
B
60Ω
VTST
–7V TO 12V
375Ω
1482 F02
RECEIVER
OUTPUT
TEST POINT
S1
CL
1k
S2
1k
VCC
1482 F03
Figure 1. Driver DC Test Load #1
Figure 2. Driver DC Test Load #2
Figure 3. Receiver Timing Test Load
DE
A
DI
RDIFF
B
A
CL1
B
CL2
VCC
1k
CD
RO
15pF
1482 F04
Figure 4. Driver/Receiver Timing Test Load
OUTPUT
UNDER TEST
500Ω
CL
S1
VCC
S2
1482 F05
Figure 5. Driver Timing Test Load
9
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