MSC8126TMP6400(2007) データシートの表示（PDF） - Freescale Semiconductor

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MSC8126TMP6400
(Rev.:2007)

Quad Digital Signal Processor

Freescale Semiconductor 

2.5.10.4 SMII Mode

Table 27. SMII Mode Signal Timing

No.

Characteristics

808

809

810

Notes:

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

• 1.1 V core.

• 1.2 V core.

1. Measured using a 5 pF load.

2. Measured using a 15 pF load.

Min Max Unit

1.0

—

ns

1.0

—

ns

1.51

6.02

ns

1.51

5.02

ns

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD

808

809

Valid

810

Valid

Figure 26. SMII Mode Signal Timing

Valid

2.5.11 GPIO Timing

Table 28. GPIO Timing

No.

Characteristics

601 REFCLK edge to GPIO out valid (GPIO out delay time)

602 REFCLK edge to GPIO out not valid (GPIO out hold time)

603 REFCLK edge to high impedance on GPIO out

604 GPIO in valid to REFCLK edge (GPIO in set-up time)

605 REFCLK edge to GPIO in not valid (GPIO in hold time)

Ref = CLKIN

Min Max

—

6.1

1.1

—

—

5.4

3.5

—

0.5

—

Ref = CLKOUT

Min Max

—

6.9

1.3

—

—

6.2

3.7

—

0.5

—

Unit

ns

ns

ns

ns

ns

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

36

Freescale Semiconductor

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