NTE8212 データシートの表示（PDF） - NTE Electronics
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NTE8212 Datasheet PDF : 4 Pages
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Functional Description:
Data Latch
The 8 flip–flops that compose the data latch are of a “D” type design. The output (Q) of the flip–flop
follows the data input (D) while the clock input (C) is high. Latching occurs when the clock (C) returns
low.
The data latch is cleared by an asynchronous reset input (CLR).
(NOTE: Clock (C) overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to three–state, non–inverting output buffers. These
buffers have a common control line (EN); enabling the buffer to transmit the data from the outputs of
the data latch (Q) or disabling the buffer, forcing the output into a high impedance state (three–state).
This high–impedance state allows the designer to connect the NTE8212 directly to the microproces-
sor bi–directional data bus.
Control Logic
The NTE8212 has four control inputs: DS1, DS2, MD and STB. These inputs are employed to control
device selection, data latching, output buffer state and the service request flip–flop.
DS1, DS2 (Device Select)
These two inputs are employed for device selection. When DS1 is low and DS2 is high (DS1 • DS2)
the device is selected. In the selected state the output buffer is enabled and the service request flip–
flop (SR) is asynchronously set.
Service Request Flip–Flop (SR)
The (SR) flip–flop is employed to generate and control interrupts in microcomputer systems. It is asyn-
chronously set by the CLR input (active low). When the (SR) flip–flop is set it is in the non–interrupting
state.
The output (Q) of the (SR) flip–flop is connected to an inverting input of a “NOR” gate. The other input
of the “NOR” gate is non–inverting and is connected to the device selection logic (DS1 • DS2). The
output of the “NOR” gate (INT) is active low (interrupting state) for connection to active low input prior-
ity generating circuits.
MD (Mode)
This input is employed to control the state of the output buffer and to determine the source of the clock
(C) to the data latch.
When MD is in the output mode (high) the output buffers are enabled and the source of clock (C) to
the data latch is from the device selection logic (DS1 • DS2).
When MD is in the input mode (low) the output buffer state is determined by the device selection logic
(DS1 • DS2) and the source of clock (C) to the data latch is the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MD = 0) and to synchronously
reset the service request (SR) flip–flop.
Note that the SR flip–flop triggers on the negative edge of STB which overrides CLR.
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