
1.1.4.2 Serial Interface
CS7410
Symbol
tclk_per
tDMs
tDMh
tDSs
tCMs
tDSh
Description
Clock period
Master-mode data setup
Master-mode data hold
Slave-mode data setup
Master chip select to clock setup
Slave mode data hold
Min Typ
66
28
28
15
28
0
Table 2. Serial Interface Characterization Data
Max
Unit
ns
ns
ns
ns
ns
ns
SER2_CLK
(CPOL=0)
SER2_CLK
(CPOL=1)
SER2_DO
(master)
SER2_DI
(slave)
SER2_CS
tCMs
tDMs
MSB
tDSs
MSB
tclk_per
tDMh
tDSh
Figure 6. Serial Interface Timing Diagram
LSB
LSB
DS553PP1
11