ML6401CS-3 データシートの表示（PDF） - Fairchild Semiconductor

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ML6401CS-3

8-Bit 20MSa/s A/D Converter

Fairchild Semiconductor 

ML6401

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

CONDITIONS

Switching Characteristics

Maximum CLK Input Frequency

Clock Duty Cycle

CLK = 13.5MHz

tPWH

tPWL

Analog To Digital Converter Inputs — CLK

CLK - 20MHz

CLK - 20MHz

Low Level Input Voltage

High Level Input Voltage

Low Level Input Current

High Level Input Current

Input Capacitance

VIL

VIH

VIL = 0.1V

VIH = VDDD – 0.1V

TIMING — DIGITAL OUTPUTS (CL = 15pF, IOL = 2mA, RL = 2kΩ, fCLK = 20MHz)

Sampling Delay

tDS

Output Hold Time

tHO

Output Delay Time

tDO

3-State Delay Time

Output Enable

3-State Delay Time

Output Disable

ANALOG TO DIGITAL CONVERTER OUTPUTS — DIGITAL

Low Level Output Voltage

High Level Output Voltage

Output Current in 3-State Mode

IOL = 2mA

IOH = 2mA

SUPPLIES

Analog Supply Current

Static

Digital Supply Current

Output Supply Current

fCLK = 20MHz

fCLK = 20MHz, CL = 0pF

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

SAMPLE

N+1

N+2

(VIN+) – (VIN–)

N

CLK

D0 TO D7

tDS

N–3

N–2

N–1

tHO

tDO

MIN

TYP

MAX UNITS

20

25

MHz

40

60

%

25

ns

25

ns

0

0.8

V

2.4

VDDD

V

–5

+5

µA

–5

+5

µA

4.0

pF

5

ns

4

12

10

ns

5

18

30

ns

10

25

ns

10

20

ns

0

0.6

V

2.4

VCCO

V

–20

+20

µA

26

34

mA

10

15

mA

4

10

mA

N+3

N+4

N

OUT

tPWH

N+1

tPWL

Figure 1. Timing Diagram

4

REV. 1.0 10/12/2000

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