TDA8020HL/C1 データシートの表示（PDF） - NXP Semiconductors.
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TDA8020HL/C1 Datasheet PDF : 28 Pages
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Philips Semiconductors
Dual IC card interface
Product specification
TDA8020HL
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Clock inputs (pins CLKIN1 and CLKIN2)
fext
external frequency applied
on CLKIN1 and CLKIN2
0
−
VIL
VIH
ti(r), ti(f)
LOW-level input voltage
HIGH-level input voltage
input transition times
VDDI > 2 V
1.5 V < VDDI < 2 V
VDDI > 2 V
1.5 V < VDDI < 2 V
0
−
0
−
0.7VDDI −
0.85VDDI −
−
−
Logic inputs (pins SAD0 and SAD1)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
ILIL
LOW-level input leakage
current
−0.3
−
0.7VDDI −
−
−
ILIH
HIGH-level input leakage
current
−
−
Ci
input capacitance
−
−
Interrupt line (pin IRQ ; open-drain; active LOW output)
VOL
LOW-level output voltage Io = 2 mA
ILH
HIGH-level leakage current
−
−
−
−
Serial data input/output (pin SDA; open-drain)
VIL
LOW-level input voltage
−0.3
−
VIH
HIGH-level input voltage
0.7VDD −
ILH
HIGH-level leakage current
−
−
IIL
LOW-level input current
depends on the pull-up resistance −
−
VOL
LOW-level output voltage IOL = 3 mA
−
−
Serial clock input (pin SCL; open-drain)
VIL
LOW-level input voltage
−0.3
−
VIH
HIGH-level input voltage
0.7VDD −
ILH
HIGH-level leakage current
−
−
IIL
LOW-level input current
depends on the pull-up resistance −
−
I2C-bus timings; see Figures 6 and 7
fSCL
clock frequency
tBUF
bus free time between a
STOP and START condition
0
−
1.3
−
tHD;STA
START condition hold time
after which first clock pulse
is generated
0.6
−
tLOW
tHIGH
tSU;STA
SCL LOW time
SCL HIGH time
set-up time START condition repeated start
1.3
−
0.6
−
0.6
−
25
MHz
0.3VDDI V
0.15VDDI V
VDDI + 0.3 V
VDDI + 0.3 V
0.1/fCLKIN ns
+0.3VDDI V
VDDI + 0.3 V
±20
µA
±20
µA
10
pF
0.3
V
10
µA
0.3VDD V
6.5
V
1
µA
−
0.3
V
0.3VDD V
6.5
V
1
µA
−
400
kHz
−
µs
−
µs
−
µs
−
µs
−
µs
2003 Nov 06
20
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