54S416T データシートの表示（PDF） - CERAMATE TECHNICAL

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54S416T

1M x 4 BANKS x 16 BITS SDRAM

CERAMATE TECHNICAL 

54S416T

SDRAM

(2) A.C Latency Characteristics

CKE to Clock Disable (CKE Latency)

DQM to Output to HI-Z (Read DQM Latency)

DQM to Output to HI-Z (Write DQM Latency)

Write Command to Input Data (Write Data Latency)

CS to Command Input ( CS Latency)

Precharge to DQ Hi-Z Lead Time

Precharge to Last Valid Data Out

Bust Stop Command to DQ Hi-Z Lead Time

Bust Stop Command to Last Valid Data Out

Read with Auto-precharge Command to Active/Ref Command

Write with Auto-precharge Command to Active/Ref Command

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

CL = 2

CL = 3

1

2

0

0

0

2

3

1

2

2

3

1

2

BL + tRP

BL + tRP

BL + tRP

BL + tRP

Cycle

Cycle + nS

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Tel:886-3-3214525

Fax:886-3-3521052

Page 18 of 47

Email: server@ceramate.com.tw

Http: www.ceramate.com.tw

Rev 1.0 Aug.21,2002

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