
MOSEL VITELIC
MSU2052/U2032
Data Memory Write Cycle Timing
T12
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
1
#PSEN
#WR
5
6
PORT2
2
ADDRESS A15- A 8
PORT0
2
3
INST Float
A 7-A 0
DATA OUT
4
ADDRESS
or Float
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1
inputs P0, P1
inputs P2, P3
Output by
MOV Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
sampled
sampled
current data
sampled
next data
Rev. 1.0 February 1998
11