3. PIN CONFIGURATION
Preliminary W6662CF
VRDC
VREF
VINR
AVSS
VING
AVSS
VINB
AVSS
NC
AVDD
CISREF
PAOUT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
NC
AVSS
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
SEN
Fig. 3-1 Pin Assignments.
4. BLOCK DIAGRAM
CISREF
VREF VRDC VRDB VRDT
VINR
Clamp
Bandgap Reference Circuit
CDS
MUX
CDS
Process
Gain/Offset
Adjust
12-bit
ADC
OEN
DOUT[11:0]
VING
Clamp
VINB
Clamp
I/P MUX
Ctrl
Configuration
Register
MUX
R
G
B
DAC
MUX
R
G
B
Weak
Drive
Serial
I/O port
control
CDSCK1 CDSCK2 SEL0 SEL1
Gain Offset
Registers Registers
ADCCLK
Fig. 4 The Block Diagram of W6662 Device.
PAOUT
PAOUTN
SCLK
SEN
SDI/SDIO
SDO/SMS
-2-